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Results: 7
Number of items: 7
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Bernard, T. A. M., Grelck, C., & Jesshope, C. (2010). On the compilation of a language for general concurrent target architectures. Parallel Processing Letters, 20(1), 51-69. https://doi.org/10.1142/S0129626410000053
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Bernard, T. A. M., Grelck, C., Hicks, M. A., Jesshope, C. R., & Poss, R. (2010). Resource-agnostic programming for many-core microgrids. In M. Forsell, & J. L. Träff (Eds.), (Hand-out) proceedings of the 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010), Ischia, Naples, Italy (pp. 28-37) http://www.par.univie.ac.at/workshop/hppc/HPPC10-Preproc.pdf
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Bernard, T., Bousias, K., Guang, L., Jesshope, C. R., Lankamp, M., van Tol, M. W., & Zhang, L. (2008). A general model of concurrency and its implementation as many-core dynamic RISC processors. In W. Najjar, & H. Blume (Eds.), 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation: IC-SAMOS 2008, July 21-24, 2008, Samos, Greece : proceedings (pp. 1-9). IEEE. https://doi.org/10.1109/ICSAMOS.2008.4664840 -
Bernard, T. A. M., Jesshope, C. R., & Knijnenburg, P. M. W. (2007). Strategies for compiling μTC to novel chip multiprocessors. In S. Vassiliadis, M. Bereković, & T. D. Hämäläinen (Eds.), Embedded Computer Systems: Architectures, Modeling, and Simulation: 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007 : proceedings (pp. 127-138). (Lecture Notes in Computer Science; Vol. 4599). Springer. https://doi.org/10.1007/978-3-540-73625-7_15
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Bernard, T., Jesshope, C. R., & Knijnenburg, P. M. W. (2006). Microthreading: model and compiler. In K. De Bosschere (Ed.), Proceedings of Advanced Computer Architecture and Compilation for Embedded Systems, ACACES 2006 (pp. 101-104). Academia Press. http://staff.science.uva.nl/~tbernard/images/papers/acaces-2006.pdf
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