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Results: 5
Number of items: 5
  • Bousias, K., Guang, L., Jesshope, C. R., & Lankamp, M. (2009). Implementation and evaluation of a microthread architecture. Journal of Systems Architecture, 55(3), 149-161. https://doi.org/10.1016/j.sysarc.2008.07.001
  • Open Access
    Bernard, T., Bousias, K., Guang, L., Jesshope, C. R., Lankamp, M., van Tol, M. W., & Zhang, L. (2008). A general model of concurrency and its implementation as many-core dynamic RISC processors. In W. Najjar, & H. Blume (Eds.), 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation: IC-SAMOS 2008, July 21-24, 2008, Samos, Greece : proceedings (pp. 1-9). IEEE. https://doi.org/10.1109/ICSAMOS.2008.4664840
  • Bernard, T., Bousias, K., de Geus, B., Lankamp, M., Zhang, L., Pimentel, A. D., Knijnenburg, P. M. W., & Jesshope, C. R. (2006). A Microthreaded Architecture and its Compiler. In Proc. of the Int. Workshop on Compilers for Parallel Computers (pp. 326-340)
  • Bousias, K., Hasansneh, N. M., & Jesshope, C. R. (2005). Instruction-level parallelism through microthreading- a scalable approach to chip multiprocessors. Computer Journal.
  • Bousias, K., & Jesshope, C. R. (2005). The Challenges of Massive On-Chip Concurrency. Lecture Notes in Computer Science, 3740, 157-170.
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