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Results: 59
Number of items: 59
  • Bernard, T., Bousias, K., de Geus, B., Lankamp, M., Zhang, L., Pimentel, A. D., Knijnenburg, P. M. W., & Jesshope, C. R. (2006). A Microthreaded Architecture and its Compiler. In Proc. of the Int. Workshop on Compilers for Parallel Computers (pp. 326-340)
  • Bell, I., Hasasneh, N., & Jesshope, C. R. (2006). Supporting Microthread Scheduling and Synchronisation in CMPs. International Journal of Parallel Programming, 34(4), 343-381. https://doi.org/10.1007/s10766-006-0017-y
  • Jesshope, C. R. (2006). μTC: an intermediate language for programming chip multiprocessors. In Proc. of the Asia-Pacific Computer Systems Architecture Conference
  • Open Access
    Erbas, C. (2006). System-level modelling and design space exploration for multiprocessor embedded system-on-chip architectures. [Thesis, fully internal, Universiteit van Amsterdam]. Amsterdam University Press.
  • Jesshope, C. R. (2005). Micro-grids- the exploitation of massive on-chip concurrency. In L. Grandinetti (Ed.), Grid Computing: A New Frontier of High Performance Computing (pp. 203-223). Elsevier.
  • Bell, I., Hasasneh, N., & Jesshope, C. R. (2005). Microgrids and Micr-contexts: Support Structures for Microthread Scheduling and Synchronisation. In Proceedings 1st MicroGrid Conference
  • Bousias, K., Hasansneh, N. M., & Jesshope, C. R. (2005). Instruction-level parallelism through microthreading- a scalable approach to chip multiprocessors. Computer Journal.
  • Bousias, K., & Jesshope, C. R. (2005). The Challenges of Massive On-Chip Concurrency. Lecture Notes in Computer Science, 3740, 157-170.
  • Jesshope, C. R. (2005). Scalable Instruction-level Parallelism. Lecture Notes in Computer Science, 3133, 383-392.
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