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Results: 59
Number of items: 59
  • Open Access
    Jesshope, C. (2008). Operating systems in silicon and the dynamic management of resources in many-core chips. Parallel Processing Letters, 18(2), 257-274. https://doi.org/10.1142/S0129626408003375
  • Open Access
    Jesshope, C. (2008). A model for the design and programming of multi-cores. In L. Grandinetti (Ed.), High performance computing and grids in action (pp. 37-55). (Advances in parallel computing; No. 16). IOS Press. http://staff.science.uva.nl/~jesshope/Papers/Multicores.pdf
  • Open Access
    Zhang, L., & Jesshope, C. (2008). On-chip COMA cache-coherence protocol for microgrids of microthreaded cores. In L. Bougé, M. Forsell, J. Larsson Träff, A. Streit, W. Ziegler, M. Alexander, & S. Childs (Eds.), Euro-Par 2007 Workshops: Parallel Processing: HPPC 2007, UNICORE Summit 2007, and VHPC 2007, Rennes, France, August 28-31, 2007 : revised selected papers (pp. 38-48). (Lecture Notes in Computer Science; Vol. 4854). Springer. https://doi.org/10.1007/978-3-540-78474-6_7
  • Hasasneh, N., Bell, I., & Jesshope, C. (2007). Asynchronous arbiter for micro-threaded chip multiprocessors. Journal of Systems Architecture, 53(5-6), 253-262. https://doi.org/10.1016/j.sysarc.2006.10.004
  • Vu, T. D., & Jesshope, C. R. (2007). Formalizing SANE Virtual Processor in thread algebra. In M. Butler, M. G. Hinchey, & M. M. Larrondo-Petrie (Eds.), ICFEM 2007 (pp. 345-365)
  • Zhang, L., & Jesshope, C. R. (2007). On-Chip COMA Cache Hierarchy for Microthreaded Architecture. In Proceedings of the 13th Annual Conference of the Advanced School for Computing and Imaging (ASCI)
  • Bernard, T. A. M., Jesshope, C. R., & Knijnenburg, P. M. W. (2007). Strategies for compiling μTC to novel chip multiprocessors. In S. Vassiliadis, M. Bereković, & T. D. Hämäläinen (Eds.), Embedded Computer Systems: Architectures, Modeling, and Simulation: 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007 : proceedings (pp. 127-138). (Lecture Notes in Computer Science; Vol. 4599). Springer. https://doi.org/10.1007/978-3-540-73625-7_15
  • Bernard, T., Jesshope, C. R., & Knijnenburg, P. M. W. (2006). Microthreading: model and compiler. In K. De Bosschere (Ed.), Proceedings of Advanced Computer Architecture and Compilation for Embedded Systems, ACACES 2006 (pp. 101-104). Academia Press. http://staff.science.uva.nl/~tbernard/images/papers/acaces-2006.pdf
  • Jesshope, C. R. (2006). Microthreading, a Model for Distributed Instruction-level Concurrency. Parallel Processing Letters, 16(2), 209-228.
  • Hasasneh, N., Bell, I., & Jesshope, C. R. (2006). Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors. In Proc. of Architecture of Computing Systems (ARCS 2006) (pp. 252-267)
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