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Results: 59
Number of items: 59
  • Jesshope, C., Hicks, M., Lankamp, M., Poss, R., & Zhang, L. (2010). Making multi-cores mainstream - from security to scalability. In B. Chapman, F. Desprez, G. R. Joubert, A. Lichnewsky, F. Peters, & T. Priol (Eds.), Parallel Computing: From Multicores and GPU's to Petascale (pp. 16-31). (Advances in Parallel Computing; Vol. 19). IOS Press. https://doi.org/10.3233/978-1-60750-530-3-16
  • Open Access
    Grelck, C., Poss, R., & Jesshope, C. (2010). Hardware virtualisation for heterogeneous many-core systems. In Intel European Research and Innovation Conference (ERIC'10), Braunschweig, Germany
  • van Tol, M. W., Jesshope, C. R., Lankamp, M., & Polstra, S. (2009). An implementation of the SANE Virtual Processor using POSIX threads. Journal of Systems Architecture, 55(3), 162-169. https://doi.org/10.1016/j.sysarc.2008.09.006
  • Bousias, K., Guang, L., Jesshope, C. R., & Lankamp, M. (2009). Implementation and evaluation of a microthread architecture. Journal of Systems Architecture, 55(3), 149-161. https://doi.org/10.1016/j.sysarc.2008.07.001
  • Jesshope, C., Lankamp, M., & Zhang, L. (2009). Evaluating CMPs and their memory architecture. In M. Berekovic, C. Müller-Schloer, C. Hochberger, & S. Wong (Eds.), Architecture of Computing Systems – ARCS 2009: 22nd International Conference, Delft, The Netherlands, March 10-13, 2009 : proceedings (pp. 246-257). (Lecture Notes in Computer Science; Vol. 5455). Springer. https://doi.org/10.1007/978-3-642-00454-4_24
  • Open Access
    Grelck, C., Herhut, S., Jesshope, C., Joslin, C., Lankamp, M., Scholz, S.-B., & Shafarenko, A. (2009). Compiling the functional data-parallel language SaC for Microgrids of Self-Adaptive Virtual Processors. In Proceedings of the 14th International Workshop on Compilers for Parallel Computing (CPC'09)
  • Jesshope, C., & Shafarenko, A. (2008). Concurrency engineering. In ACSAC 2008: 13th IEEE Asia-Pacific Computer Systems Architecture Conference: Proceedings (pp. 1-8). IEEE. https://doi.org/10.1109/APCSAC.2008.4625426
  • Open Access
    Zhang, L., & Jesshope, C. (2008). On-chip COMA cache-coherence protocol for microgrids of microthreaded cores. In L. Bougé, M. Forsell, J. Larsson Träff, A. Streit, W. Ziegler, M. Alexander, & S. Childs (Eds.), Euro-Par 2007 Workshops: Parallel Processing: HPPC 2007, UNICORE Summit 2007, and VHPC 2007, Rennes, France, August 28-31, 2007 : revised selected papers (pp. 38-48). (Lecture Notes in Computer Science; Vol. 4854). Springer. https://doi.org/10.1007/978-3-540-78474-6_7
  • Open Access
    Jesshope, C. (2008). A model for the design and programming of multi-cores. In L. Grandinetti (Ed.), High performance computing and grids in action (pp. 37-55). (Advances in parallel computing; No. 16). IOS Press. http://staff.science.uva.nl/~jesshope/Papers/Multicores.pdf
  • Open Access
    Jesshope, C., Philippe, J.-M., & van Tol, M. (2008). An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency. In M. Bereković, N. Dimopoulos, & S. Wong (Eds.), Embedded Computer Systems: Architectures, Modeling, and Simulation: 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008 : proceedings (pp. 218-228). (Lecture Notes in Computer Science; Vol. 5114). Springer. https://doi.org/10.1007/978-3-540-70550-5_25
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