Task-Level Redundancy vs Instruction-Level Redundancy against Single Event Upsets in Real-Time DAG Scheduling

Authors
Publication date 2021
Book title 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip : MCSoC 2021
Book subtitle 20-23 December 2021, Singapore : proceedings
ISBN
  • 9781728187525
ISBN (electronic)
  • 9781665438605
Event IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip
Pages (from-to) 373-380
Publisher Los Alamitos, CA: IEEE Computer Society
Organisations
  • Faculty of Science (FNWI) - Informatics Institute (IVI)
Abstract
Real-time cyber-physical systems have become ubiquitous. As such systems are often mission-critical, designers must include mitigations against various types of hardware faults, including Single Event Upsets (SEU). SEUs can be mitigated using both software and hardware approaches. When using software approaches, the application designer needs to select the appropriate redundancy level for the application. We propose the use of task-level redundancy for SEU detection, aiming at applications structured as a Directed Acyclic Graph (DAG) of tasks. This work compares existing instruction-level redundancy against task-level redundancy using the UPPAAL model checking tool in SMC mode. Our comparison shows that task-level redundancy implemented using Dual Modular Spatial Redundancy and Checkpoint-Restart offers significantly lower deadline miss ratios when slack is limited. While task-level redundancy usually performs better or equal, we also show that rare cases exist where long running DAG application benefit more from instruction-level redundancy.
Document type Chapter
Language English
Published at https://doi.org/10.1109/MCSoC51149.2021.00062
Other links https://www.proceedings.com/62454.html
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