A characterization of the SPARC T3-4 system
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| Publication date | 2011 |
| Series | arXiv.org/cs, arXiv:1106.2992 |
| Number of pages | 21 |
| Publisher | Ithaca, NY, USA: Cornell University Library |
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| Abstract |
This technical report covers a set of experiments on the 64-core SPARC T3-4 system, comparing it to two similar AMD and Intel systems. Key characteristics as maximum integer and floating point arithmetic throughput are measured as well as memory throughput, showing the scalability of the SPARC T3-4 system. The performance of POSIX threads primitives is characterized and compared in detail, such as thread creation and mutex synchronization. Scalability tests with a fine grained multithreaded runtime are performed, showing problems with atomic CAS operations on such physically highly parallel systems.
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| Document type | Report |
| Language | English |
| Published at | |
| Downloads |
2011_T3-4_report_ArXiv_1.pdf
(Final published version)
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