Application-specific FPGAs: cryptographic agility through customized reconfigurable architectures

Authors
Publication date 2023
Book title 2023 IEEE International Parallel and Distributed Processing Symposium workshops (IPDPSW 2023)
Book subtitle St. Petersburg, Florida, USA, 15-19 May 2023
ISBN
  • 9798350312003
ISBN (electronic)
  • 9798350311990
Event 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023
Pages (from-to) 121-124
Number of pages 4
Publisher Piscataway, NJ: IEEE
Organisations
  • Faculty of Science (FNWI) - Informatics Institute (IVI)
Abstract

Cryptography is an important feature in modern devices, especially in Internet-of-Things (IoT) networks. When a deployed cryptographic algorithm is not secure anymore, then devices that use it are immediately vulnerable to attacks and secret information can be exposed or devices themselves could be compromised. Because of the widespread need of cryptography, several application domains would certainly benefit from the use a small embedded Field-Programmable Gate Array (eFPGA) for cryptography. To this end, Mentens et al. proposed an eFPGA tailored towards symmetric-key algorithms and designed to be more resource-efficient than general-purpose Lookup Table (LUT) based FPGA structures for the configuration of symmetric-key algorithms, while showing a similar performance.In this paper, we extend that earlier work (that was mostly focused on the architectural aspect of the eFPGA) and we complete it considering also the routing overhead of the proposed solution. We use an open-source design flow to estimate the potential of cryptography-tailored eFPGA structures and compare them with classical LUT-based FPGAs. With our design flow, that we describe in details in the paper, we are able to precisely estimate the overhead due to the routing. Our results confirm that for symmetric ciphers, just like for many other applications, the routing overhead is predominant. The methodology we followed for estimation and the precise estimation of the routing overhead that we provide are a fundamental information for the future exploration of cryptography-tailored eFPGAs.

Document type Conference contribution
Language English
Published at https://doi.org/10.1109/IPDPSW59300.2023.00031
Other links https://www.proceedings.com/70179.html https://www.scopus.com/pages/publications/85169299378
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