Maurer computers for pipelined instruction processing
| Authors | |
|---|---|
| Publication date | 2008 |
| Journal | Mathematical Structures in Computer Science |
| Volume | Issue number | 18 | 02 |
| Pages (from-to) | 373-409 |
| Organisations |
|
| Abstract | We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing using Maurer machines, basic thread algebra and program algebra. We show that stored programs are executed as intended with these micro-architectures. We believe that this work provides a new mathematical approach to the modelling of micro-architectures and the verification of their correctness and the anticipated speed-up results. |
| Document type | Article |
| Published at |
https://doi.org/10.1017/S0960129507006548
(Final published version)
|
| Downloads | |
| Permalink to this page | |
