System-level runtime mapping exploration of reconfigurable architectures

Authors
  • K. Bertels
Publication date 2009
Book title 2009 IEEE International Symposium on Parallel & Distributed Processing (IPDPS 2009): Rome, Italy, 23-29 May 2009
ISBN
  • 9781424437511
Event 16th Reconfigurable Architectures Workshop (RAW 2009), Rome, Italy
Pages (from-to) 1-8
Publisher Piscataway, NJ: IEEE
Organisations
  • Faculty of Science (FNWI) - Informatics Institute (IVI)
Abstract
Dynamic reconfigurable systems can evolve under various conditions due to changes imposed either by the architecture, or by the applications, or by the environment. In such systems, the design process becomes more sophisticated as all the design decisions have to be optimized in terms of runtime behaviors and values. Runtime mapping exploration allows to explore reconfigurable systems at runtime to optimize task mappings in order to adapt to the changing behavior of the application(s), the architecture, or the environment. Performing such explorations at runtime enables a system to be more efficient in terms of various design constraints such as performance, chip area, power consumption, etc. Towards this goal, in this paper, we present a model that facilitates runtime mapping exploration of reconfigurable architectures. A case study of an MJPEG application shows that the presented model can be used to perform runtime exploration of various functional and non-functional design parameters.
Document type Conference contribution
Published at http://doi.ieeecomputersociety.org/10.1109/IPDPS.2009.5161199
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