However, although an individual DRISC core can perform remarkably well with sufficient concurrency, as a part of the many-core system, it suffers from the sharing of on-chip interconnections and off-chip pins in the context of massive parallelism. The resultant bandwidth problem is shared by other many-core research designs and is detrimental to system scalability. This thesis extends this prior work by investigating system performance and by broadening the application of this processor design.
Domain-specific computing may also exploit multiple cores to accelerate jobs. Real-time processing is a good example of this but perhaps with modest numbers of cores. The question explored here is whether we can enhance specific single or multi-thread real-time task performance while still meeting timing requirement and maintaining a high efficiency, or even under a general workload. The results from the time-multiplexed execution of both the normal task and periodic real-time benchmarks highlight the benefits of the proposed strategy with hardware prioritization, and prove the wisdom of reserving thread slots instead of cores.
Series: ASCI dissertation series 302
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