- A high-level power model for MPSoC on FPGA
- IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
- Book/source title
- 2011 IEEE IPDPS Workshops & PhD Forum (IPDPSW)
- Book/source subtitle
- 25th IEEE International Parallel & Distributed Processing Symposium : 16-20 May, 2011, Anchorage, Alaska, USA
- Pages (from-to)
- Los Alamitos, CA: IEEE Computer Society
- ISBN (electronic)
- Document type
- Conference contribution
- Faculty of Science (FNWI)
- Informatics Institute (IVI)
This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, e.g., commonly-used instruction-set simulator (ISS) based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of Micro blaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.
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