- Evaluating CMPs and their memory architecture
- Lecture Notes in Computer Science
- Pages (from-to)
- Document type
- Faculty of Science (FNWI)
- Informatics Institute (IVI)
Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of technology. This paper presents a CMP architecture that supports automatic mapping and dynamic scheduling of threads leaving the binary code devoid of any explicit communication. The thrust of this approach is to produce binary code that is divorced from implementation parameters, yet, which still gives good performance over future generations of CMPs. A key component of this abstract processor architecture is the memory system. This paper evaluates the memory architectures, which must maintain performance across a range of targets.
- go to publisher's site
- Proceedings title: Architecture of Computing Systems - ARCS 2009: 22nd International Conference, Delft, the Netherlands, March
10-13, 2009: proceedings
Place of publication: Berlin
Editors: M. Berekovic, C. Müller-Schloer, C. Hochberger, S. Wong
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