- On-chip COMA cache-coherence protocol for microgrids of microthreaded cores
- Lecture Notes in Computer Science
- Pages (from-to)
- Document type
- Faculty of Science (FNWI)
- Informatics Institute (IVI)
This paper describes an on-chip COMA cache coherency protocol to support the microthread model of concurrent program composition. The model gives a sound basis for building multi-core computers as it captures concurrency, abstracts communication and identifies resources, such as processor groups explicitly and where mapping and scheduling is performed dynamically. The result is a model where binary compatibility is guaranteed over arbitrary numbers of cores and where backward binary compatibility is also assured. We present the design of a memory system with relaxed synchronisation and consistency constraints that matches the characteristics of this model. We exploit an on-chip COMA organisation, which provides a flexible and transparent partitioning between processors and memory. This paper describes the coherency protocol and consistency model and describes work undertaken on the validation of the model and the development of a co-simulator to the Microgrid CMP emulator.
- go to publisher's site
- Proceedings title: Euro-Par 2007 workshops: Parallel processing: HPPC 2007, UNICORE Summit 2007, and VHPC 2007, Rennes, France,
August 28-31, 2007: Revised selected papers
Place of publication: Berlin
Editors: L. Bougé, M. Forsell, J.L. Träff, A. Streit, W. Ziegler, M. Alexander, S. Childs
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